POWER ANALYSIS IN 4T DRAM CELL USING SLEEP AND SELF CONTROLLABLE VOLTAGE LEVEL TOPOLOGIES
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Abstract
Due to the modern developments in the field of very Large Scale Integrated circuits, the designers are much focused to design a good performance circuit with high speed and low power. Nowadays it is becoming a challenge to design a circuit with a better performance, high speed and a low cost device. Due to the increase in the demand of VLSI, CMOS technology plays a vital role. Dynamic Random Access Memory is the volatile memory, which is used in wide ranges of applications. In this paper, low power techniques like sleep transistor logic and Self Voltage Controllable Logic (SCVL).A 4T DRAM cell using the above logics has been designed and power has been analyzed. The simulation is done using Tanner 13.1.EDA tool.
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Low power, DRAM, Volatile, Sleep, SCVL
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