An Efficient AES Algorithm for Cryptography using VLSI

Abstract

Purpose: The objective of this paper is to examine the encryption process used in information security. Information security has become a most crucial component in data correspondence framework. Encryption is a fundamental tool used for Information security. Organization of all classes relies on these encryption algorithms to protect their data. Initially DES- Data Encryption Standard algorithm was used it is a symmetric block cipher which means a same key is used for both encryption and decryption. The main disadvantage with that algorithm is it is easily crackable and is vulnerable to attacks. The calculations comparing to DES, Triple DES are remunerating with tremendous memory spaces and can’t be executed on the equipment stage. AES - Advanced Encryption Standard algorithm has replaced DES in number of ways. AES is an efficient cryptographic algorithm which uses various key lengths and outperformed compared to DES. By utilizing field programmable entryway clusters (FPGA’S) we can execute equipment stage circumstance inferable from its reconfiguration nature, low charge and publicizing Space. The RIJNDAEL cryptography algorithmic guideline might be a square figure used to scramble/decode advanced data and is equipped for utilizing crypto graphical keys of 28,192 and 256 bits.

Methodology: With the concept centered on key expansion with dual stage design this method is proposed. Having an aim of finding out the result and consequence of using a number of round blocks on utilization of power, the dual stage scheme has been used. The high-speed designs focus to hike the throughput by using unrolling and pipelining. As our design is capable of finishing a key expansion of 128-bit keys internally the control logic to execute simultaneous encryptions will result in a further round block over the power users because of dynamic design. In the prevailing DOR schemes for finishing a single round, it takes eleven clock cycles and it uses output data bus for sending the encrypted data.

Findings: The findings indicate that the simulation result of 128 data input test vectors. The 128-bit input data is encrypted using 4 byte key at each round and generates the secret code. The simulation is performed using Xilinx software and it is tested using test bench code. The simulation result shows the conversion of 128 plain texts to cipher text. The findings also show the decrypted output of 128 cipher text. It follows the reverse process of encryption. At each round, the encrypted key is separated from original data at the last round the original plain text is recovered from cipher text. Compared to DES the throughput is increased and delay is reduced in the AES algorithm.

Originality/value: In this paper, the empirical results show the basic details required to implement the AES encryption algorithm. The needs of implementation including the primary input and primary output of the design, power notation and conventions were explained. To understand the proper flow, the design's general implementation flow has been discussed.