Design of a Low Power Multiplier and Divider for 64 Bit ALU

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Published Sep 8, 2021


Arithmetic logic unit (ALU) is the integral part of computer processor, which perform arithmetic and logical operations. This paper deals with the design of 64-bit arithmetic logic unit (ALU). The ALU is designed with the architectures which have high performance. The ALU modules are independent of each other and are realized using Verilog HDL. Functionalities of the Design are verified by compilation and simulation. Test vectors are created to check whether the calculated and output values are same or not. ModelSim simulator software is used for simulation. For synthesis Intel Quartus prime software is used.

How to Cite

YEGNESHWAR YADHAV S. (2021). Design of a Low Power Multiplier and Divider for 64 Bit ALU. SPAST Abstracts, 1(01). Retrieved from
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Article Details


64 - bit ALU, Full adder

[1] JVR Ravindra, Gangadhar Reddy Ramireddy and Harikrishna Kamatham, “Design of Ultra Low Power Full Adder using Modified Branch Based Logic Style,” IEEE European Modelling Symposium, 2013, pp. 691-696.
[2] T. Esther Rani, M.A. Rani and R. Rao, “AREA optimized low power arithmetic and logic unit,” IEEE International Conference on Electronics Computer Technology, April 2011, pp. 224–228.
[3] Rajesh Parihar, Nidhi Tiwari, Aditya Mandloi and Dr.Binod Kumar, “An Implementation of 1-Bit Low Power Full Adder Based on Multiplexer and Pass Transistor Logic,” IEEE International Conference on Information Communication and Embedded System, 2014, pp. 101- 103.
[4] S. M. Swamynathan,”Design and Analysis of FPGA based 32 bit ALU using Reversible Gates”, ICEICE at 2017.
[5] Ancy J. Raj and P.V. Ashwin (2015), “Performance Improvement of ALU using D3L Logic”, Elsevier, Procedia Computer Science 46, 1341.
[6] Bhukya Shankar, “Delay, Power performance of 8-Bit ALU Using Carry Look-Ahead Adder with High Vt Cell”, IJRASET at 2018.
[7] S. B. Shirol, “A Novel Design and Implementation of 32-Bit Hybrid ALU “, IEEE Conference at 2019.
[8] Manit kantawala, “Design and Implementation of 8 Bit and 16 Bit ALU using Verilog Language “, IJRASET at 2018.
[9] Jithesh R.Shinde, “An Optimization Design Approach for Arithmetic Logic Unit “, ICICCT at 2020.
[10] L. Dhulipalla and A. Deepak, “Design and implementation Of 4-bit ALU using FINFETS for nano scaletechnology,” IEEE International Conference on Nanoscience, Engineering and Technology, November 2011, pp. 190–195.
GM2- Microsystems & Nanotechnology