Design of a Low Power Multiplier and Divider for 64 Bit ALU

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Published Sep 8, 2021
YEGNESHWAR YADHAV S

Abstract

Arithmetic logic unit (ALU) is the integral part of computer processor, which perform arithmetic and logical operations. This paper deals with the design of 64-bit arithmetic logic unit (ALU). The ALU is designed with the architectures which have high performance. The ALU modules are independent of each other and are realized using Verilog HDL. Functionalities of the Design are verified by compilation and simulation. Test vectors are created to check whether the calculated and output values are same or not. ModelSim simulator software is used for simulation. For synthesis Intel Quartus prime software is used.

How to Cite

YEGNESHWAR YADHAV S. (2021). Design of a Low Power Multiplier and Divider for 64 Bit ALU. SPAST Abstracts, 1(01). Retrieved from https://spast.org/techrep/article/view/190
Abstract 4 |

Article Details

Keywords

64 - bit ALU, Full adder

References
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Section
GM2- Microsystems & Nanotechnology